US Patent

Methods and systems for ordering instructions using future values

Patent number: 7747993
Filing date: Dec 30, 2004
Issue date: Jun 29, 2010
Application number11/026,425


Conference and Workshop



ISCA 2015

(Portland, USA)

Görkem Aşılıoğlu, Zhaoxiang Jin, Murat Köksal, Omkar Javeri, and Soner Önder. 2015. LaZy superscalar. In Proceedings of the 42nd Annual International Symposium on Computer Architecture (ISCA '15). ACM, New York, NY, USA, 260-271. DOI=10.1145/2749469.2750409


ICS 2015

(Newport Beach, USA)

Zhaoxiang Jin, Görkem Aşilioğlu, and Soner Önder. 2015. Mower: A New Design for Non-blocking Misprediction Recovery. In Proceedings of the 29th ACM on International Conference on Supercomputing (ICS '15). ACM, New York, NY, USA, 285-294. DOI=10.1145/2751205.2751228


ICS 2014

(Munich, Germany)

Hui Meen Nyew, Nilufer Onder, Soner Onder, and Zhenlin Wang. 2014. Verifying micro-architecture simulators using event traces. In Proceedings of the 28th ACM international conference on Supercomputing (ICS '14). ACM, New York, NY, USA, 323-332. DOI=10.1145/2597652.2597680


CGO 2014

(Orlando, USA)

Shuhan Ding, John Earnest, and Soner Önder. 2014. Single Assignment Compiler, Single Assignment Architecture: Future Gated Single Assignment Form*; Static Single Assignment with Congruence Classes. In Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO '14). ACM, New York, NY, USA, , Pages 196 , 12 pages. DOI=10.1145/2544137.2544158


CC 2010

(Paphos,Cyprus)

Shuhan Ding and Soner Önder.Unrestricted code motion: A program representation and transformation algorithms based on future values. In Rajiv Gupta, editor, Compiler Construction, volume 6011 of Lecture Notes in Computer Science, pages 26-45. Springer Berlin / Heidelberg, 2010. 10.1007/978-3-642-11970-5_3. [bib| Original Publication at Springer| pdf ]


CF 2008

(Ischia, Italy)

Peng Zhou and Soner Õnder.Improving single-thread performance with fine-grain state maintenance. In Proceedings of the 5th conference on Computing frontiers, CF '08, pages 251-260, New York, NY, USA, 2008. ACM. [ bib | Original Publication at ACM | pdf ]


ICS 2006

(Cairns, Australia)

Changpeng Fang, Steve Carr, Soner Önder, and Zhenlin Wang.Feedback-directed memory disambiguation through store distance analysis. In Proceedings of the 20th annual international conference on Supercomputing, ICS '06, pages 278-287, New York, NY, USA, 2006. ACM. [ bib | Original Publication at ACM  | pdf ]


CC 2006

(Vienna, Austria)

Changpeng Fang, Steve Carr, Soner Önder, and Zhenlin Wang.Path-based reuse distance analysis. In Alan Mycroft and Andreas Zeller, editors, Compiler Construction, volume 3923 of Lecture Notes in Computer Science, pages 32-46. Springer Berlin / Heidelberg, 2006. 10.1007/11688839_4. [ bib | Original Publication at Springer | pdf]


PACT 2005

(St Louis, USA)

Changpeng Fang, S. Carr, S. Önder, and Zhenlin Wang.Instruction based memory distance analysis and its application to optimization. In Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on, pages 27 - 37, 2005. [ bib | Original Publication at IEEE | pdf]


ICS 2005

(Boston, USA)

Peng Zhou, Soner Önder, and Steve Carr.Fast branch misprediction recovery in out-of-order superscalar processors. In Proceedings of the 19th annual international conference on Supercomputing, ICS '05, pages 41-50, New York, NY, USA, 2005. ACM. [ bib | Original Publication at ACM | pdf]



CF 2005

(Ischia, Italy)

Steve Carr and Soner Önder.A case for a working-set-based memory hierarchy. In Proceedings of the 2nd conference on Computing frontiers, CF '05, pages 252-261, New York, NY, USA, 2005. ACM. [ bib | Original Publication at ACM | pdf ]


MSP 2004

(Washington DC,USA)

Changpeng Fang, Steve Carr, Soner Önder, and Zhenlin Wang.Reuse-distance-based miss-rate prediction on a per instruction basis. In Proceedings of the 2004 workshop on Memory system performance, MSP '04, pages 60-68, New York, NY, USA, 2004. ACM. [ bib | Original Publication at ACM | pdf ]


PACT 2002

(Charlottesville, Virginia, USA)

Soner Önder.Cost effective memory dependence prediction using speculation levels and color sets. In Parallel Architectures and Compilation Techniques, 2002. Proceedings. 2002 International Conference on, pages 232 - 241, September 2002. [ bib | Original Publication at IEEE |pdf]


CC 2002

(Grenoble,France)

Siddharth Rele, Santosh Pande, Soner Önder, and Rajiv Gupta.Optimizing static power dissipation by functional units in superscalar processors. In R. Horspool, editor, Compiler Construction, volume 2304 of Lecture Notes in Computer Science, pages 85-100. Springer Berlin / Heidelberg, 2002. 10.1007/3-540-45937-5_19. [ bib | Original Publication at Springer | pdf]


INTERACT-5 2001

(Monterrey Mexico,USA)

Bedy, M.J., Carr, S., Önder, S. and Sweany, P.,Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches, in Interaction between Compilers and Computer Architectures, G. Lee and P.-C. Yew ed., Kluwer Academic Publishers, 2001 pp. 69-88. [bib | pdf ]


ICS 2001

(Naples, Italy)

Soner Önder and Rajiv Gupta.Load and store reuse using register file contents. In Proceedings of the 15th international conference on Supercomputing, ICS '01, pages 289-302, New York, NY, USA, 2001. ACM. [ bib | Original Publication at ACM | pdf ]


Europar 2001

(Manchaster, UK)

Soner Önder and Rajiv Gupta.Instruction wake-up in wide issue superscalars. In Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing, Euro-Par '01, pages 418-427, London, UK, 2001. Springer-Verlag. [ bib | Original Publication at Springer | pdf]


PACT 1999

(Newport Beach, California,USA)

Soner Õnder, Jun Xu, and Rajiv Gupta.Caching and predicting branch sequences for improved fetch effectiveness. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, PACT '99, pages 294-, Washington, DC, USA, 1999. IEEE Computer Society. [ bib | Original Publication at ACM/IEEE | pdf]


MICRO 1999

(Haifa, Israel)

Soner Õnder and Rajiv Gupta.Dynamic memory disambiguation in the presence of out-of-order store issuing. In Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, MICRO 32, pages 170-176, Washington, DC, USA, 1999. IEEE Computer Society. [ bib | Original Publication at ACM/IEEE | pdf]


PACT 1998

(Paris, France)

Soner Õnder and Rajiv Gupta.Superscalar execution with dynamic data forwarding. In Parallel Architectures and Compilation Techniques, 1998. Proceedings. 1998 International Conference on, pages 130 -135, October 1998. [ bib | Original Publication at IEEE | pdf]


ICCL 1998

(Chicago, Illinois, USA)

Soner Õnder and Rajiv Gupta.Automatic generation of microarchitecture simulators. In Computer Languages, 1998. Proceedings. 1998 International Conference on, pages 80 -89, May 1998. [ bib | Original Publication at IEEE | pdf | Longer version pdf]


HiPC 1995

(New Delhi, India)

Soner Õnder and Rajiv Gupta. SINAN - A Forwarding Multithreaded Architecture. International Conference on High Performance Computing, pages 347-354, New Delhi, India, December 1995 [pdf]



Book Chapter



J. Bastian and S. Õnder. Specification of Intel IA-32 using an Architecture Description Language, IFIP International Federation for Information Processing, 2005, Volume 176, Architecture Description Languages, Pages 151-166. (pdf)


Senkul, P., Õnder, N., Õnder, S., Maden, E., Nyew, H. M., Discovering Patterns for Architecture Simulation by using Sequence Mining in Pattern Discovery Using Sequence Data Mining: Applications and Studies. Prandeep Kumar, P. Radha Krishna, S, Bapi Raju, (IGI Global).


Õnder, S., "ADL++:Object-Oriented Specification of Complicated Instruction Sets and Microarchitectures" in Processor Description Languages, Volume 1 (Systems on Silicon). Prabhat Mishra and Nikil Dutt, (Morgan Kaufmann (Elsevier) Publishers, Burlington MA, June 2, 2008), Chapter 10, 247-274.



Journal

JILP 2002

Soner Önder and Rajiv Gupta. Dynamic memory disambiguation in the presence of out-of-order store issuing. J. Instruction-Level Parallelism, 4, 2002. [ bib | Original Publication at JILP | pdf]