Publications


Evaluating the impacts of hugepage on virtual machines, Xiaolin Wang,  Taowei Luo, Jiangyuan Hu, Zhenlin Wang and Yingwei Luo,  Science China Information Sciences 60:012103, 2017.

  

Optimized Locality-aware Memory Management for Key-value Cache, Xiameng Hu, Xiaolin Wang,  Lan Zhou, Yingwei Luo, Chen Ding, Song Jiang, and Zhenlin Wang,  IEEE Transactions on Computers (TC'17), VOl.: 66, Issue: 5, May 1 2017.


Optimal Symbiosis and Fair Scheduling in Shared Cache, Xianmeng Hu, Xiaolin Wang, Yechen Li, Yingwei Luo,  Chen Ding, and Zhenlin Wang, IEEE Transactions on Parallel and Distributed Systems (TPDS'17). Vol.: 28, Issue: 4, April 1, 2017. 


Kinetic Modeling of Data Eviction, Xiameng Hu, Xiaolin Wang, Yechen Li, Lan Zhou, Yingwei Luo, Chen Ding, and Zhenlin Wang, Proceedings of the 2016 USENIX Annual Technical Conference (ATC'16), Dever, CO, June 22-24, 2016.


Barrier-Aware Warp Scheduling for Throughput Processors, Yuxi Liu, Zhigin Yu, Lieven Eeckhout, Vijay Janapa Reddi, Yingwei Luo, Xiaolin Wang, Zhenlin Wang and Chengzhong Xu, Proceedings of he 2016 International Conference on Supercomputing (ICS'16), Istanbul, Turkey, June 1-3, 2016.


Dynamic Memory Balancing for Virtualization, Zhigang Wang, Xiaolin Wang, Fan Hou, Yingwei Luo, and Zhenlin Wang, ACM Transactions on Architecture and Code Optimization, Vol. 13, 1, Article 2, April 2016, (TACO'16).


LAMA: Optimized Locality-aware Memory Allocation for Key-value Cache, Xiameng Hu, Xiaolin Wang, Yechen Li, Lan Zhou, Yingwei Luo, Chen Ding, Song Jiang, and Zhenlin Wang, Proceedings of the 2015 USENIX Annual Technical Conference (ATC'15), Santa Clara, CA, July 8-10, 2015.


Modeling Cross-Architecture Co-Tenancy Performance Interference. Wei Kuang, Laura E. Brown, and Zhenlin Wang, Proceedings of the 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid'15), Shenzhen, China, May 4-7, 2015.


Optimal Footprint Symbiosis in Shared Cache, Xiaolin Wang, Yechen Li, Yingwei Luo, Xiameng Hu, Jacob Brock, Chen Ding, and Zhenlin Wang, Proceedings of the 15th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid'15), Shenzhen, China, May 4-7, 2015 


Transfer Learning-based Co-run Scheduling for Heterogeneous Datacenters,  Wei Kuang, Laura E. Brown, and Zhenlin Wang, Proceedings of the Twenty-Ninth AAAI Conference on Artificial Intelligence (AAAI'15), PhD Consortium, Austin, Texas, USA, Jan. 25-29, 2015.


Selective Switching Mechanism in Virtual Machines via Support Vector Machine and Transfer Learning, Wei Kuang, Laura E. Brown, and Zhenlin Wang, Machine Learning, July, 2014. 

 

Verifying Micro-architecture Simulators using Event Traces, Hui Meen Nyew, Nilufer Onder, Soner Onder, and Zhenlin Wang, The 28th ACM International Conference on Supercomputing (ICS’14), Munich, Germany, June 10- 13, 2014. 

 

Revisiting Memory Management on Virtualized Environments, Xiaolin Wang, Lingmei Weng, Yingwei Luo, and Zhenlin Wang, ACM Transactions on Architecture and Code Optimization, Volume 10 Issue 4 No. 48, Dec. 2013 ( TACO'13, Presented at HiPEAC'14).

 

Towards Eliminating Memory Virtualization Overhead, Xiaolin Wang, Lingmei Weng, Yingwei Luo, and Zhenlin Wang, APPT'13 (See the TACO'13 paper for the extension of this work).

 

A First-Order Logic Based Framework for Verifying Simulations, Hui Meen Nyew, Nilufer Onder, Soner Onder and Zhenlin Wang, AAAI Conference on Artificial Intelligence (AAAI'13),  PhD Consortium, June, 2013.

 

Dynamic Cache Partitioning Based on Hot Page Migration, Xiaolin Wang, Xiang Wen, Yechen Li, Zhenlin Wang, Yingwei Luo, and Xiaoming Li, Frontiers of Computer Science, 2012 6(4): 363-372, 2012.

 

Low Cost Working Set Size Tracking, Weiming Zhao, Xinxin Jin, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, and Xiaoming Li, Proceedings of the 2011 USENIX Annual Technical Conference (ATC'11), ortland, OR, June 15-17, 2011 (short paper).

 

Efficient LRU-Based Working Set Size Tracking, Weiming Zhao, Xinxin Jin, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, and Xiaoming Li, Computer Science Technical Report, CS-TR-11-01, March, 20011.

 

Selective Hardware/Software Memory Virtualization, Xiaolin Wang, Jian Rui Zang, Zhenlin Wang, Yingwei Luo, and Xiaoming Li, Proceedings of the 2011 ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE'11), Newport Beach, CA, March 9-11, 2011.

 

Predicting Remove Reuse Distance Patterns in UPC Applications, Steven Vormwald, Wei Wang, Steve Carr, Steve Seidel, and Zhenlin Wang, Proceedings of the ACM Fourth Conference on Partitioned Global Address Space Programming Models (PGAS'10), NY, Oct. 12-15, 2010.

 

ScaleUPC: A UPC Compiler for Multi-Core Systems, Weiming Zhao and Zhenlin Wang, Proceedings of the ACM Third Conference on Partitioned Global Address Space Programming Models (PGAS'09), Ashburn, VA, Oct. 5-8, 2009.

 

Dynamic Memory Balancing for Virtual Machines, Weiming Zhao and Zhenlin Wang, Proceedings of the 2009 ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (VEE'09), Washington, DC, March 11-13, 2009.

 

ScaleUPC: A UPC Compiler for Multi-Core Systems, Weiming Zhao and Zhenlin Wang, Michigan Tech University, Technical Report CS-TR 08-02, Sept., 2008.

 

Live and Incremental Whole-System Migration of Virtual Machines Using Block-Bitmap, Yingwei Luo, Binbin Zhang, Xiaolin Wang, Zhenlin Wang, Yifeng Sun, and Haogang Chen, IEEE Cluster 2008, Tsukuba, Japan, Sept.28-Oct.1, 2008.

 

A Transparent Remote Paging Model for Virtual Machines, Haogang Chen, Yingwei Luo, Xiaolin Wang, Binbin Zhang, Yifeng Sun and Zhenlin Wang, International Workshop on Virtualization Technology (IWVT in conjunction with ISCA'08), Beijing, June 2008.

 

Feedback-directed Memory Disambiguation Through Store Distance Analysis, Changpeng Fang, Steve Carr, Soner Onder, and Zhenlin Wang, The 20th ACM International Conference on Supercomputing (ICS'06), Cairns, Australia, June 28- July 1, 2006.

Path-based Reuse Distance Analysis
, Changpeng Fang, Steve Carr, Soner Onder, and Zhenlin Wang, Proceedings of the 15-th International Conference on Compiler Construction (CC'06), Vienna, Austria, March, 2006.

Instruction Based Memory Distance Analysis and its Application
, Changpeng Fang, Steve Carr, Soner Onder, and Zhenlin Wang, Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT '05), St. Louis, September 17-21, 2005.

Cooperative Caching with Keep-Me and Evict-Me
, Jennifer B. Sator, Subramaniam Venkiteswaran, Kathryn S. McKinley, and Zhenlin Wang, the 9th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT-9), In conjunction with 11th International Symposium on High-Performance Computer Architecture (HPCA-11), San Francisco, Febuary, 2005

The Garbage Collection Advantage: Improving Program Locality
, Xianglong Huang, Stephen M. Blackburn, Kathryn S. McKinley,  J. Eliot B. Moss, Zhenlin Wang, and Perry Cheng,   Proceedings of the 19th ACM Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA '04), Vancouver, Canada, October, 2004.

Reuse-distance-based Miss-rate Prediction on a Per Instruction Basis
, Changpeng Fang, Steve Carr, Soner Onder, and Zhenlin Wang, the third Workshop on Memory System Performance (MSP) in conjunction with PLDI 2004, Washington DC, June 2004.

Combining Cooperative Software/Hardware Prefetching and Cache Replacement
, Zhenlin Wang, Kathryn S. McKinley, and Doug Burger,  IBM Austin CAS Center for Advanced Studies Conference, Austin, TX, February 2004.

Cooperative Hardware/Software Caching for Next-Generation Memory Systems
, PhD Dissertation, University of Massachusetts, Amherst, Sept., 2003.

Guided Region Prefetching: A Cooperative Hardware/Software Approach, Zhenlin Wang, Doug Burger, Steven K. Reinhardt , Kathryn S. McKinley, Charles C. Weems, Proceedings of the Thirtieth International Symposium on Computer Architecture (ISCA '03), San Diego, CA, June 9-11, 2003 (This version contains a couple of non-critical corrections to our published one).

Using the Compiler to Improve Cache Replacement Decisions, Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, and Charles C. Weems, Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT '02), Charlottesville, Virginia, September 22-25, 2002.

Compiling for the Impulse Memory Controller, Xianglong Huang, Zhenlin Wang, and Kathryn S. McKinley, Proceedings of International Conference on Parallel Architectures and Compilation Techniques (PACT '01), Barcelona, Spain, September 8-12, 2001.

On Memory Behavior of Scalars in Embedded Multimedia Systems, Osman S. Unsal, Zhenlin Wang, Israel Koren, C. Mani Krishna, and Csaba Andras Moritz, Proceedings of WMPI'01, Workshop on Memory Performance Issues, Goteborg, Sweden, June, 2001.

Improving Replacement Decisions in Set-Associative Caches, Zhenlin Wang, Kathryn S. McKinley, and Arnold L. Rosenberg, Proceedings of MASPLAS'01, The Mid-Atlantic Student Workshop on Programming Languages and Systems, IBM Watson Research Center, Hawthorne, NY, April, 2001.

Improving Replacement Decisions in Set-Associative Caches, Zhenlin Wang, Kathryn S. McKinley, and Arnold L. Rosenberg, University of Massachusetts at Amherst, Technical Report TR 01-02, March, 2001.