introduction to computing systems

from bits & gates to C & beyond

Figure 3.11 A two-input decoder

Figure 3.12 A 2-to-1 mux

Figure 3.13 A four-input mux

Figure 3.15 Gate-level description of a full adder

Figure 3.16 A circuit for adding two 4-bit binary numbers

Figure 3.18 An R-S latch

Figure 3.19 A gated D latch

Figure 3.20 A four-bit register

Figure 3.21 A 2²-by-3-bit memory

Figure 3.27 A state diagram

Figure 3.31 State diagram for the traffic danger sign controller

Figure 3.32 Sequential logic circuit implementation of Figure 3.30

The LC3.