Computer Organization & Design

The Hardware / Software Interface

Third Edition

Patterson and Hennessey

Figure B.3.2 A two-input multiplxor.

Figure B.3.4 The PLA for implementing the logic function described above.

Figure B.5.1 The 1-bit logical unit for AND and OR.

Figure B.5.5 Adder hardware for the carry out signal.

Figure B.5.6 A 1-bit ALU that performs AND, OR, and addition.

Figure B.5.7 A 4-bit ALU constructed from 4 1-bit ALUs

Figure B.5.8 A 1-bit ALU that performs AND, OR, and addition on a and b or a and not-b.

Figure B.5.9 A 1-bit ALU that performs AND, OR, and addition on a and b or not-a and not-b.

Figure B.5.10 A 1-bit ALU that performs AND, OR, and addition on a and b or not-b, and a 1-bit ALU for the most significant bit.

Figure B.5.11 A 4-bit ALU constructed from 3 copies of the 1-bit ALU in the top of Figure B.5.10 and one 1-bit ALU in the bottom of that figure.

Figure B.8.1 A pair of cross-coupled NOR gates can store an internal value.

Figure B.8.2 A D latch implemented with NOR gates.

Figure B.8.4 A D flip-flop with a falling-edge trigger.

Figure B.8.8 The implementation of two read ports for a register file with 4 registers can be done with a pair of 4-1 multiplexors each 32-bits wide.

Figure B.8.9 The write port for a register file is implemented with a decoder that is used with the write signal to generate the C input to the registers.

Figure B.9.1 A 32Kx8 SRAM showing the fifteen address lines (32K = s¹⁵) and eight data inputs, the three control lines, and the eight data outputs.

Figure B.9.2 Four three-state buffer are used to forma multiplexor.

Figure B.9.3 The basic structure of a 4x2 SRAM consists of a decoder that selects which pair of cells to activate.

Figure B.10.2 The graphical representation of the two-state traffic light controller.

One Cycle Microarchitecture

Multi-Cycle Microarchitecture