Computer Organization & Design

The Hardware / Software Interface

Third Edition

Patterson and Hennessey

The multi-cycle microarchitecture implementation of the MIPS instruction subset.

ALU

ALU Control

Memory

Shift 32 bits 2 bits left (for beq)

Shift 26 bits 2 bits left (for j)

Sign extend 16 bits to 32 bits

Initial memory A MIPS program to compute the sum of the first 10 integers (answer = 55).

Entire CPU

To run the simulation, first download the entire CPU (above), then create a file called "memfile" containing the contents of the "Initial memory" link above. The file names are case sensitive.

Then start up JLS and load the MultiCycle.jls circuit file. Simply running the simulator in the background will load the initial memory file into the memory element, then run the program in the memory until the HALT is executed. Check the contents of the data memory to see that the answer (55) was indeed stored at word address 0xa (corresponding to byte address 40).

To see the step-by-step operation of the circuit, start up JLS, load MultiCycle.jls, then make the simulator window visible, set some probes or make some registers visible, then step the simulation at some convenient time step. A clock cycle is 2000 time units, so a reasonable time step might be 500. Change the scale factor on the signal trace to something like 10 to make the trace easier to understand.

Some notes about the circuit:

Only 256 32-bit words of memory are implemented. The upper bits of the address are simply ignored.
Memory elements read/write 32 bit words, and word addresses must be used to address them. Hence the lower two bits of the address are not used (i.e., only the word address component is routed to the address pins of the memory element).
The general registers ($1-$31) are initialized to the same integer value as their designation (e.g., register $7 has initial value 7).
A HALT instruction (op code 63 = 0x3f) has been added. All other instruction bits are ignored. The simulation stops immediately when a HALT is decoded - the last clock cycle is not completed.
The control is implemented as a state machine using the state machine element in JLS. When stepping execution, you can see what state the state machine is currently in by moving the cursor over the "Control" element in the circuit and looking at the blue message bar above the circuit.