Computer Organization & Design

The Hardware / Software Interface

Third Edition

Patterson and Hennessey

The one cycle microarchitecture implementation of the MIPS instruction subset.

ALU

ALU Control

Instruction Memory

Data Memory

Control

Initial instruction memory A MIPS program to compute the sum of the first 10 integers (answer = 55).

Initial data memory Data memory for MIPS program above (initial values).

Entire CPU

To run the simulation, first download the entire CPU (above), then create two files, one called "instmem" containing the contents of the "Initial instruction memory" link above, the other called "datamem" containing the contents of the "Initial instruction memory" link above. The file names are case sensitive.

Then start up JLS and load the OneCycle.jls circuit file. Simply running the simulator in the background will load the two initial memory files into the corresponding memory elements, then run the program in the instruction memory until the HALT is executed. Check the contents of the data memory element to see that the answer (55) was indeed stored at word address 4 (corresponding to byte address 16).

To see the step-by-step operation of the circuit, start up JLS, load OneCycle.jls, then make the simulator window visible, set some probes or make some registers visible, then step the simulation at some convenient time step. A clock cycle is 2500 time units, so a reasonable time step might be 500. Change the scale factor on the signal trace to something like 10 to make the trace easier to understand.

Some notes about the circuit:

Only 256 32-bit words of instruction and data memory are implemented. The upper bits of the address are simply ignored.
Memory elements read/write 32 bit words, and word addresses must be used to address them. Hence the lower two bits of the address are not used (i.e., only the word address component is routed to the address pins of the memory elements).
The general registers ($1-$31) are initialized to the same integer value as their designation (e.g., register $7 has initial value 7).
A HALT instruction (op code 63 = 0x3f) has been added. All other instruction bits are ignored. The simulation stops immediately when a HALT is fetched - the last clock cycle is not completed.